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The core takes PCM audio samples via a channel and outputs them in S/PDIF format

to a port. Audio samples are encapsulated into S/PDIF words (adding preamble,

parity, channel status and validity bits) and transmitted in biphase-mark encoding

(BMC) with respect to an external master clock. Note that a minor change to the

SpdifTransmitPortConfig

function would enable internal master clock generation

(e.g. when clock source is already locked to desired audio clock).

Sample frequencies 44.1, 48, 88.2, 96, 176.4, 192 kHz

Master clock ratios 128x, 256x, 512x

Module module_spdif_tx

Figure 15:

S/PDIF

Capabilities

3.10.1 Clocking

PORT

PORT D-type

MCLKXCORE Tile

S/PDIF

DATA

via clock block

Figure 16:

D-Type Jitter

Reduction

The S/PDIF signal is output at a rate dictated by the external master clock. The

master clock must be 1x 2x or 4x the BMC bit rate (that is 128x 256x or 512x

audio sample rate, respectively). The minimum master clock frequency for 192kHz

is therefore 24.576MHz.

This resamples the master clock to its clock domain (oscillator), which introduces

jitter of 2.5-5 ns on the S/PDIF signal. A typical jitter-reduction scheme is an

external D-type ﬂip-ﬂop clocked from the master clock (as shown in the preceding

diagram).

3.10.2 Usage

The interface is normal channel with streaming built-ins (

outuint

inuint

). Data

format is 24-bit left-aligned in a 32-bit word: 0x12345600

The following protocol is used on the channel:

3.10.3 Output stream structure

The stream is composed of words with the following structure shown in Figure 18.

The channel status bits are 0x0nc07A4, where c=1 for left channel, c=2 for right

channel and n indicates sampling frequency as shown in Figure 19.

REV 6.1

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